1. Field of the Invention
The present invention relates to an electric signal connecting device and a probe assembly for use in checking circuits in a plurality of semiconductor chips formed on a semiconductor wafer in the process of producing LSI and other electronic devices or in checking circuits in liquid crystal and other electronic devices. The present invention is used in the so-called probing test for, for example, measuring the electric conduction of semiconductor chips en bloc by bringing vertical probes into contact with circuit terminals (pads) arranged on the semiconductor chips while they are still in a wafer state.
2. Description of Prior Art
The degree of integration of electronic devices has improved keeping pace with the progress in semiconductor technology, and the area occupied by circuit interconnection in each semiconductor chip formed on a semiconductor wafer keeps on increasing. As a result, the number of circuit terminals (pads) has increased on each semiconductor chip, and in keeping pace therewith the contraction of pad area, and the miniaturization of pad arrangement due to narrowing of pad pitch are progressing. At the same time, chip size packing of loading bare chips in circuit boards without enclosing semiconductor chips into package is becoming the main stream. For this reason, it becomes necessary by all means to check property and determine quality in the wafer state before dividing it into semiconductor chips.
In particular, an issue arising out of the miniaturization of pad arrangement (narrowing of pitch) is that the structure of probe for obtaining electric conductivity by bringing it into contact with the pads of semiconductor chips at the time of electric property tests or circuit test of electronic devices must be matched to the miniaturization of pad arrangement, and various measuring means are used to cope with this progress in miniaturization of pad arrangement.
For example, one of such means is one that makes a probe assembly made by area arranging a plurality of needle probes having a resiliently transforming part resiliently transforming in response to outside forces intervene between the pads of semiconductor chips to be tested and the testing device. As a means of electrically connecting this probe assembly and the test circuit of semiconductor chips, a printed wiring board called “probe card” is used. A past example of such circuit testing technology involving such a probe is, for example, the invention disclosed in the Japanese Patent Disclosure No. 2002-298297 and Japanese Patent Disclosure No. 2003-075503.
Generally in a probe card wherein a needle probe having a cantilever structure consisting of cantilever beams, the tip of probe coming into contact with the pad of semiconductor chips is narrow pitched, but in the base part in contact with the probe card, due to the radially expanding arrangement of the probe from the tip, a coarse pitch could be used and it was possible to fix probes to the circuit terminals of a probe card by soldering and similar connecting means. However, this cantilever structure had a problem of damaging the pads due to shifts in the horizontal direction of the tip that serve as the contact point when it comes into contact with the pad, or resulting in a fall in the measurement yield due to the tip falling off the pad. In addition, there were problems in that only a tip could be measured at a time and that the precision of fixing each probe varied resulting in a difficulty of controlling the contact pressure to a constant level.
In a vertical probe replacing this cantilever structure, in other words, in a vertical probe wherein the probe is fixed vertically to the circuit terminals of probe card, it is necessary that the pad pitch on a semiconductor chip and the circuit terminal pitch on a probe card have the same pitch interval. However, the miniaturization of circuit patterns on a probe card which is a printed wire board is limited by fabrication technology, and therefore, it is difficult for the area occupied by circuit terminals and wiring width to satisfy the requirements matching the pad pitch, and also because of a limit to the pitch interval for soldering, it was impossible to vertically fix a vertical probe to the probe card according to the pad pitch of the semiconductor chip as miniaturization progressed.
Thus, in a probe card the proportion of its plane area being occupied by the area of circuit terminals and the width of circuit interconnection is important and obstructs the narrowing of pitch of circuit terminals. Accordingly, it was decided to adopt the means of maintaining the number of vertical probes by using a multilayered printed wiring board for the probe card, by arranging circuit terminals in a grid, in two lines or zigzag form and by electrically connecting the wiring between layers via through-holes. However, due to a large area represented by these through-holes, the presence of through-holes was an obstacle for narrowing the pitch of arranging circuit terminals. Thus, any attempt to fix vertical probes to a probe card was plagued by the difficulty of narrowing the pitch of circuit terminals and required an advanced technology in soldering and a large number of manual operations leading to high costs of manufacturing. In order to solve these problems, the inventors of the present invention propose a vertical probe assembly and have already proposed a probing device as an electric signal connecting device based on the use of such vertical probe assembly (see the Patent Reference 1 and the Patent Reference 2).
FIG. 1 is a perspective view showing a vertical probe assembly as a past example proposed by the inventors of the present invention. As the perspective view in FIG. 1 shows, this vertical probe assembly 200 already proposed (see, for example, the Patent Reference 1) consists of erecting a plurality of vertical probes 205 between two parallel upper and lower square insulating boards (or insulation films) 201 and 202. The two upper and lower insulating boards 201 and 202 are kept apart at a fixed interval being blocked by a stage in the middle of the vertical probe 205, and the pitch arrangement of vertical probes 205 is made to agree with the pitch arrangement of pads on the semiconductor chips to be tested. The upper and lower tips of each vertical probe 205 protrude slightly the insulating boards 201 and 202 and serve as electric contact terminals 203, and a curved part 204 is created in the intermediate part to provide resiliency against outside force applied on the probe in the vertical direction and to absorb distortions. At the same time, the deformation of the curved part 204 serves as the source of restoring force of spring, and this restoring force of spring turns into contact pressure between the top of the spring force probe and the pad to give electric conductivity. This curved part 204 is created at different vertical positions for each row so that the vertical probes 205 arranged at the right angle may not come into contact each other. And each vertical probe 205 has a square section, and is inserted into square holes created at opposite positions of the upper and lower insulating boards 201 and 202 so that it may move vertically but does not rotate constituting an anti-rotating structure.
A probing device having such a vertical probe assembly (see, for example, the Patent Reference 2) is constituted as shown in the perspective view of FIG. 2. Specifically, above this vertical probe assembly 200. a semiconductor wafer on which a large number of semiconductor chips to be tested not shown have been formed is set on a wafer stage while the chip pads are kept upside down. On the other hand, below the vertical probe assembly 200, a connecting structure 206 is provided to enter into contact with the vertical probe of this probe assembly 200. This connecting structure 206 is connected with a probe card 208 through a flexible flat cable 207. And the wiring on the connecting structure 206 side of the flexible flat cable 207 is wired by the same narrow pitch as the chip pads. And the end of wiring enables the wiring terminals to come into contact en bloc with the vertical probes of the vertical probe assembly 200. And the wiring pitch interval on the probe card 208 side of the flexible flat cable 207 is extended in such a way that the circuit wiring terminals on the probe card 208 may be soldered.
And the wafer stage (not shown) and the vertical probe assembly 200 can be moved in the X-Y-Z-θ direction. And the vertical probe assembly 200, once positioned and brought into contact en bloc with the wiring terminal of a flexible flat cable provided on the connecting structure 206, need not be moved until the end of the wafer test. Here, the connecting structure 206 plays the role of a socket for connecting with vertical probes by fixing the wiring terminal surface of the flexible flat cable 207 facing upward horizontally. As the details of this connecting structure have already been proposed, the description thereof is omitted here.
The wafer stage is moved in this condition, one of the semiconductor chips is positioned on the vertical probe assembly, and respectively a plurality of chip pad and the upper contact terminals of the vertical probe assembly are connected en bloc. This enables to connect electrically narrow pitch semiconductor chips and probe cards, and drastic improvement of functions as probing device contributes greatly to promote higher integration of semiconductor devices.
As described above, probing devices in which a vertical probe assembly proposed already by the inventors of the present invention can measure even semiconductor chips of a narrowed pad pitch of 45 μm for example. Moreover, due to the possibility of automatically assembling probes without resorting to soldering, it is possible to mass produce them at low costs, and due to the possibility of vertically contacting en bloc the chip pads, it is possible to uniformly control contact pressure on all the probes. These are important advantages obtained from them.
Nevertheless, this probing device is not different from others in that a plurality of semiconductor chips formed on a semiconductor wafer are tested successively one after another, and it is necessary to move the wafer stage by one tip for each test. On the other hand, the recent trend in the production of semiconductor wafers is for larger diameter (for example, 300 mm in diameter), and the number of semiconductor chips formed on a semiconductor wafer ranges from several tens to several hundreds representing an increasingly higher density. As a result, the time required to test a piece of semiconductor wafer becomes considerable, and the demand is rising for a probing device provided with multiple array of vertical probe assembly (hereinafter referred to as “multiple array vertical probe assembly”) capable of testing simultaneously all the semiconductor chips on a wafer without moving the wafer stage. However, in the case of a wafer on which 200 chips each having 100 pads are formed for example, 100×200=20,000 signal wiring cables will be required for each multiple array vertical probe assembly, and it is difficult to efficiently draw such a number of signal wiring cables from a multiple array vertical probe assembly and connect them to outside testing apparatuses.
On the other hand, if a multiple array vertical probe assembly is to be used for a burn in test, due to a high temperature environment of approximately 12° C. in which it will be placed, the effect of thermal expansion that is not an important issue for testing a chip at a time by a separate row probe assembly will grow in importance, and pitch discrepancy will develop between the pitch of pads formed on a silicon wafer and the pitch of vertical probes planted on insulating board made of a resin film and the like. In particular, as the position of vertical probes moves closer to the perimeter of the wafer, the discrepancy of pitch of vertical probes will be cumulated, grow larger and it will become impossible to probe.
Lately a further higher speed and mass en bloc treatment are required. For example, a probe assembly capable of bringing simultaneously contacts into contact with all the pads on a waver with a diameter of 12 inches (wafer of 300 mm in diameter) and of coping with high frequency. With regards to this requirement for higher speed, the following points will be important:
(1) Reduce electric capacity, and for this purpose reduce the area of the probe for the entirety.
(2) Shorten as much as possible the distance between the test circuit and the pads on a wafer.
(3) Reduce noises resulting from magnetic interference generated by probes and wiring cables.
(4) Long distance between contacts and wiring cables opposite thereto.
With regards to wiring lines between probe assemblies and test circuits, the connection of a large number of wiring lines is required. And as a result of narrowing of pitch, a high arraying accuracy of contacts is also required because contacts and pads face each other over a large area.
With regards to a growing number of wiring lines and narrowing of pitch, for example, the number of contacts in a wafer wherein 600 chips having 200 pads each are formed totals as many as 120,000. It seems possible to solve this number problem by applying a further developed method of the method described in the Japanese Patent Disclosure 2003-075503 to the prior printed wiring board. While the pitch provided by a flat cable is narrow 30 μm pitch, an important issue is how to cope with the wiring of test circuits in view of such narrow pitch contacts. And supposing that a contact force of 5 g is applied on each of the 120,000 contacts, a total force of approximately 600 kg will act on the whole probe assembly. Such a force is likely to create a problem of deformation of mechanical parts.
The present invention is made to satisfy these requirements, and its object is to provide an electric signal connecting device with a multiple array structure of vertical probe assembly wherein the problem of thermal expansion and signal wiring are solved and probe assembly used therein so that a plurality of chips may be subjected en bloc at the same time to a probing test or a burn-in test at the time of testing the property of semiconductor chips and other similar circuits which are now becoming increasingly dense as a result of high integration of electronic devices.